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1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2012. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners 12-bit, 250ksps low-power adcs with single-ended and differential inputs and multiple input channels ISL26320, isl26321, isl26322, isl26323, isl26324, isl26325, isl26329 the ISL26320/21/22/23/24/25/29 family of sampling sar-type adcs feature excellent linearity over supply and temperature variations, and offer versions with 1-, 2-, 4- and 8-channel single-ended inputs, and 1-, 2- and 4-channel differential inputs. a proprietary input multiplexer and combination buffer amplifier reduces the input drive requirements, resulting in lower cost and reduced board space. specified measurement accuracy is maintained with input signals up to vdd. members of the ISL26320/21/22/23/24/25/29 family of low-power adcs offer pinout intercompatibility, differing only in the analog inputs, to support quick replication of proven layouts across multiple design platforms. the serial digital interface is spi compatible and is easily interfaced to popular fpgas and microcontrollers. power consumption is limited to 15mw at a sampling rate of 250ksps, and an operating current of just 8 a typical between conversions, when configured for auto powerdown mode. the ISL26320/21/22/23/24/25/29 feature up to 5kv human body model esd survivability and are available in the popular soic and tssop packages. performance is specified for operation over the full industrial temperature range (-40c to +125c). features ? pin-compatible family allows easy design upgrades ? excellent differential non-linearity (0.7lsb max) ? low thd: -86db (typ) ? simple spi-compatible serial digital interface ? low 3ma operating current ? power-down current between conversions 8 a (typ) ? +5.25v to +2.7v supply ? excellent esd survivability: 5kv hbm, 350v mm, 2kv cdm applications ? industrial process control ? energy measurement ? multichannel data acquisition systems ? pressure sensors ? flow controllers figure 1. functional block diagram june 8, 2012 fn8273.0
ISL26320, isl26321, isl26322, isl26323, isl26324, isl26325, isl26329 2 fn8273.0 june 8, 2012 application block diagram pin-compatible family model resolution (bits) speed (khz) analog input input channels isl26310 12 125 differential 1 isl26311 12 125 single-ended 1 isl26312 12 125 differential 2 isl26313 12 125 single-ended 2 isl26314 12 125 differential 4 isl26315 12 125 single-ended 4 isl26319 12 125 single-ended 8 ISL26320 12 250 differential 1 isl26321 12 250 single-ended 1 isl26322 12 250 differential 2 isl26323 12 250 single-ended 2 isl26324 12 250 differential 4 isl26325 12 250 single-ended 4 isl26329 12 250 single-ended 8
ISL26320, isl26321, isl26322, isl26323, isl26324, isl26325, isl26329 3 fn8273.0 june 8, 2012 ordering information part number (notes 1, 2, 3) part marking description temp. range (c) package (pb-free) pkg dwg # resolution (bits) speed (khz) input (se/diff) input channels ISL26320fbz 26320 fbz 12 250 diff 1 -40 to +125 8 ld soic m8.15 isl26321fbz 26321 fbz 12 250 se 1 -40 to +125 8 ld soic m8.15 isl26322fvz 26322 fvz 12 250 diff 2 -40 to +125 16 ld tssop m16.173 isl26323fbz 26323 fbz 12 250 se 2 -40 to +125 8 ld soic m8.15 isl26324fvz 26324 fvz 12 250 diff 4 -40 to +125 16 ld tssop m16.173 isl26325fvz 26325 fvz 12 250 se 4 -40 to +125 16 ld tssop m16.173 isl26329fvz 26329 fvz 12 250 se 8 -40 to +125 16 ld tssop m16.173 notes: 1. add ?-t*? suffix for tape and reel. please refer to tb34 7 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ special pb-free material sets, molding compounds/die attach material s, and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for ISL26320 , isl2632 1 , isl26322 , isl26323 , isl2632 4 , isl26325 , isl26329 . for more information on msl please see techbrief tb363 .
ISL26320, isl26321, isl26322, isl26323, isl26324, isl26325, isl26329 4 fn8273.0 june 8, 2012 pin configurations ISL26320 (8 ld soic) top view isl26321 (8 ld soic) top view isl26323 (8 ld soic) top view isl26322 (16 ld tssop) top view isl26324 (16 ld tssop) top view isl26325 (16 ld tssop) top view isl26329 (16 ld tssop) top view
ISL26320, isl26321, isl26322, isl26323, isl26324, isl26325, isl26329 5 fn8273.0 june 8, 2012 pin descriptions pin name pin number description ISL26320 isl26321 isl26322 isl26323 isl26324 isl26325 isl26329 vdd 1 1 1 1 1 1 1 positive supply voltage gnd 2 2 2, 4 2 2, 4 2, 4 2, 4 ground vref - 3 3 - 3 3 3 reference voltage input ain0+ - - 5 - 5 - - differential analog input, positive ain0- - - 6 - 6 - - differential analog input, negative ain1+ - - 7 - 7 - - differential analog input, positive ain1- - - 8 - 8 - - differential analog input, negative ain2+ - - - - 10 - - differential analog input, positive ain2- - - - - 9 - - differential analog input, negative ain3+ - - - - 12 - - differential analog input, positive ain3- - - - - 11 - - differential analog input, negative ain0 - 4 - 3 - 5 5 single-ended analog input ain1 - - - 4 - 7 6 single-ended analog input ain2 - - - - - 10 7 single-ended analog input ain3 - - - - - 12 8 single-ended analog input ain4 - - - - - - 9 single-ended analog input ain5 - - - - - - 10 single-ended analog input ain6 - - - - - - 11 single-ended analog input ain7 - - - - - - 12 single-ended analog input sdi 5 5 13 5 13 13 13 serial interface data input sdo 6 6 14 6 14 14 14 serial interface data output sclk 7 7 15 7 15 15 15 serial interface clock input cnv 8 8 16 8 16 16 16 conversion control input nc - - 9, 10, 11, 12 - - 6, 8, 9, 11 - no connect ain+ 3 - - - - - - differential analog input, positive ain- 4 - - - - - - differential analog input, negative
ISL26320, isl26321, isl26322, isl26323, isl26324, isl26325, isl26329 6 fn8273.0 june 8, 2012 absolute maximum ratings thermal information ain+, ain-, vref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd-0.3 to v dd +0.3v digital inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd-0.3 to v dd +0.3v vdd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 6v gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd-0.3 to +0.3v esd rating human body model (per mil-std-883 method 3015.7) . . . . . . . . . . . 5000v machine model (per jesd22-a115). . . . . . . . . . . . . . . . . . . . . . . . . . 350v charged device model (per jesd22-c101) . . . . . . . . . . . . . . . . . . . . . . 2000v latch-up (tested per jesd-78b; class 2, level a) . . . . . . . . . . . . . . . . . . . . . . 100ma thermal resistance (typical) ja (c/w) jc (c/w) 8 ld soic (notes 4, 5) . . . . . . . . . . . . . . . . . 98 48 16 ld tssop (notes 4, 5) . . . . . . . . . . . . . . 92 29 maximum power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80mw maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . +150c maximum storage temperature range . . . . . . . . . . . . . -65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www .int er sil.com/pbfree/pb-f reer ef lo w .asp operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +125c v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7v to +5.25v caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb3 79 for details. 5. for jc , the ?case temp? location is taken at the package top center. electrical specifications vref = vdd v, vdd = 2.7v to 5v, v cm = vdd/2, sclk = 20mhz and t a = -40c to +125c (typical performance at +25c), unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +125c. symbol parameter test level or notes min (note 6) typ max (note 6) units analog inputs number of input channels ISL26320, isl26321 1 isl26322 2 isl26323 2 isl26324, isl26325 4 isl26329 8 input voltage range differential inputs (ainx+ - ainx-) is -v ref (min) and +v ref (max) 0v ref v ainx, single-ended inputs 0 v ref v common mode input voltage range differential inputs v ref /2 ? 0.2 v ref/2 v ref /2 + 0.2 v average input current 2.5 a c in input capacitance 4pf channel-channel crosstalk f in = 100khz v in = fs, other channels = 0v -86 db voltage reference v refex external reference input voltage range 2 2.5 v dd v i refin average input current 200 220 a c refin effective input capacitance 10 pf dc accuracy resolution (no missing codes) 12 bits dnl differential nonlinearity error -0.7 +0.7 lsb inl integral nonlinearity error -0.7 +0.7 lsb gain error -6 6 lsb gain error matching -2 2 lsb offset error -6 6 lsb
ISL26320, isl26321, isl26322, isl26323, isl26324, isl26325, isl26329 7 fn8273.0 june 8, 2012 offset error matching -2 2 lsb psrr power supply rejection ratio 70 db dynamic performance snr signal-to-noise notes: v in = fs-0.1db, f in = 10khz differential inputs 73.4 db single-ended inputs 73.4 db sinad signal-to-noise + distortion notes: v in = fs-0.1db, f in = 10khz differential inputs 73.1 db single-ended inputs 73.1 db thd total harmonic distortion notes: v in = fs-0.1db, f in = 10khz differential inputs -86 db single-ended inputs -86 db sfdr spurious-free dynamic range notes: v in = fs-0.1db f in = 20khz 96 db bw -3db input bandwidth 2.5 mhz t ad sampling aperture delay 12 ns t jit sampling aperture jitter 25 ps power supply requirements v dd supply voltage 2.7 5.25 v i dd supply current 3 3.5 ma pd power consumption normal operation 15 17.5 mw ipd power-down current auto power-down mode 8 50 a istby standby mode current auto sleep mode 0.4 ma digital inputs v ih 0.7 vdd v v il 0.2 v dd v v oh i oh = -1ma vdd-0.4 v v ol i ol = 1ma 0.2 v dd v i ih , i il input leakage current -100 100 na serial clock frequency 20 mhz timing specifications (note 7) t sclk sclk period (in rac mode) 50 ns t sclk sclk period (in rsc, rdc modes) 50 100 ns t data safe data transfer time after conversion state begins 1.6 s t csb_sclk csb falling low to sclk rising edge 40 ns t sdi_su sdi setup time with respect to positive edge of sclk 10 ns t sdi_h sdi hold time with respect to positive edge of sclk 10 ns t sdo_v sdout valid time with respect to negative edge of sclk 25 ns t sdoz_d sdout to high impedance state after cnv rising edge (or last sclk falling edge) note 8 85 ns t acq acquisition time when fully powered up 400 ns electrical specifications vref = vdd v, vdd = 2.7v to 5v, v cm = vdd/2, sclk = 20mhz and t a = -40c to +125c (typical performance at +25c), unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +125c. (continued ) symbol parameter test level or notes min (note 6) typ max (note 6) units
ISL26320, isl26321, isl26322, isl26323, isl26324, isl26325, isl26329 8 fn8273.0 june 8, 2012 t acq acquisition time in auto sleep mode 1.7 s t acq acquisition time in auto power down mode 150 s t sclkh sclk high time 20 ns t sclkl sclk low time 20 ns t cnv cnv pulse width 100 ns notes: 6. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 7. the device may become nonresponsive if the minimum acquisition times are not met in their respective modes, requiring a powe r cycle to restore normal operation. 8. transition time to high impedance state is dominated by rc loading on the sdout pin. specified value is measured using equiv alent loading shown in figure 2. electrical specifications vref = vdd v, vdd = 2.7v to 5v, v cm = vdd/2, sclk = 20mhz and t a = -40c to +125c (typical performance at +25c), unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +125c. (continued ) symbol parameter test level or notes min (note 6) typ max (note 6) units figure 2. equivalent load circuit for digital output testing
ISL26320, isl26321, isl26322, isl26323, isl26324, isl26325, isl26329 9 fn8273.0 june 8, 2012 typical performance characteristics t a = +25c, v dd = 5v, v ref = 5v, f sample = 250khz, f sclk = 20mhz, unless otherwise specified. figure 3. differential nonlinearity (dnl) vs code figure 4. integral nonlinearity (inl) vs code figure 5. dnl distribution vs temperature figure 6. inl distribution vs temperature figure 7. gain error vs supply voltage and temperature figure 8. offset error vs supply voltage and temperature -1.00 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 -2000 -1000 0 1000 2000 code dnl (lsbs) -1.00 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 -2000 -1000 0 1000 2000 code inl (lsbs) -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 -40 -20 0 20 40 60 80 100 120 temperature (c) dnl negative dnl positive dnl -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 -40 -20 0 20 40 60 80 100 120 temperature (c) inl negative inl positive inl -40 -20 0 20 40 60 80 100 120 temperature (c) gain error (lsb) -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 5.0v 5.25v 2.7v 3.3v -40 -20 0 20 40 60 80 100 120 temperature (c) -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 3.3v 5.0v 5.25v 2.7v offset error (lsb)
ISL26320, isl26321, isl26322, isl26323, isl26324, isl26325, isl26329 10 fn8273.0 june 8, 2012 figure 9. aperture delay vs supply voltage figure 10. supply current vs voltage and temperature figure 11. supply current vs sampling rate (v dd = 5v) figure 12. shutdown currents vs voltage and temperature figure 13. snr and sinad vs supply voltage and temperature figure 14. thd vs supply voltage and temperature typical performance characteristics t a = +25c, v dd = 5v, v ref = 5v, f sample = 250khz, f sclk = 20mhz, unless otherwise specified. (continued) 0 5 10 15 20 25 2.7 3.2 3.7 4.2 4.7 5.2 aperture delay (ns) supply voltage 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 -40 -20 0 20 40 60 80 100 120 supply current (ma) temperature (c) 5.25v 3.3v 5.0v 2.7v 0.0 0.5 1.0 1.5 2.0 2.5 100 1k 10k 100k sample rate (sps) supply current (ma) auto power down mode auto sleep mode normal mode 0 5 10 15 20 25 30 35 40 45 50 -40 -20 0 20 40 60 80 100 120 temperature (c) shutdown current ( a) 5.25v 3.3v 5.0v 2.7v 70 71 72 73 74 75 -40 -20 0 20 40 60 80 100 120 temperature (c) 5.25v 3.3v 5.0v 2.7v snr/sinad (db) -90 -88 -86 -84 -82 -80 -40 -20 0 20 40 60 80 100 120 temperature (c) thd (db) 5.25v 3.3v 5.0v 2.7v
ISL26320, isl26321, isl26322, isl26323, isl26324, isl26325, isl26329 11 fn8273.0 june 8, 2012 figure 15. snr and sinad vs input frequency figure 16. thd vs input frequency figure 17. single-tone fft figure 18. shorted input histogram typical performance characteristics t a = +25c, v dd = 5v, v ref = 5v, f sample = 250khz, f sclk = 20mhz, unless otherwise specified. (continued) 55 60 65 70 75 100 1k 10k 100k 1m input frequency (hz) snr/sinad (db) snr sinad -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 100 1k 10k 100k 1m input frequency (hz) thd (db) -160 -140 -120 -100 -80 -60 -40 -20 0 0 25000 50000 75000 100000 125000 frequency (hz) amplitude (db) snr = 73.6db thd = -87.6db sinad = 73.4db sfdr = 89.1db enob = 11.4 0 10,000 20,000 30,000 40,000 50,000 60,000 70,000 -3 -2 -1 0 1 2 3 code 65,536 codes 0 codes 0 codes hits
ISL26320, isl26321, isl26322, isl26323, isl26324, isl26325, isl26329 12 fn8273.0 june 8, 2012 circuit description the ISL26320/21/22/23/24/25/29 family of 12-bit adcs are low-power successive approximation-type (sar) adcs with 1-, 2-, 4-, or 8-c hannels and a choice of single-ended or differential inputs. the high-impedance buffered input simplifies interfacing to sensors and external circuitry. the entire ISL26320/21/22/23/24/25/29 family follows the same base pinout and differs only in the analog input pins, allowing the user to replicate the basic board layout across multiple platforms with a minimum redesign effort. the simple serial digital interface is compatible with popular fpgas and microcontrollers and allows direct conversion control by the cnv pin. functional description the ISL26320/21/22/23/24/25/29 devices are sar (successive approximation register) analog-to-digital converters that use capacitor-based charge redistribution as their conversion method. these devices include an on-chip power-on reset (por) circuit to initialize the internal digital logic when power is applied. an on-chip oscillator provides the master clock for the conversion logic. the cnv signal controls when the converter enters into its signal acquisition time (cnv = 0), and when it begins the conversion sequence after the signal has been captured (cnv = 1). the converters include a configuration register that can be accessed via the serial port. the configuration register has various bits to indicate which channel (where applicable) is selected, to activate the auto-power-down feature where the adc is shut down between conversions, or to output the configuration register contents along with the data conversion word whenever a conversion word is read from the serial port. the serial port supports three different modes of reading the conversion data. these will be discussed later in this data sheet. figures 19 and 20 illustrate simplified representations of the converter analog section for differential and single-ended inputs, respectively. during the acquisition phase (cnv = 0) the input signal is presented to the cs samples capacitors. to properly sample the signal, the cnv signal must remain low for the specified time. when cnv is taken high (cnv = 1), the switches that connect the sampling capacitors to the input are opened and the control logic begins the successive approximation sequence to convert the captured signal into a digital word. the conversion sequence timing is determined by the on-chip oscillator. adc transfer function the ISL26320, the isl26322, and the isl26324 feature differential inputs with output data coding in two's complement format (see table 1). the size of one lsb in these devices is (2*vref)/4096. figure 21 illustrates the ideal transfer function for these devices. the isl26321, isl26323, isl26325, and isl26329 feature single-ended inputs with output coding in binary format (see table 2). the size of one lsb in these devices is vref/4096. figure 22 illustrates the ideal transfer function for these devices. figure 19. architectural block diagram, differential input figure 20. architectural block diagram, single-ended
ISL26320, isl26321, isl26322, isl26323, isl26324, isl26325, isl26329 13 fn8273.0 june 8, 2012 analog inputs some members of the ISL26320/21/22/23/24/25/29 family feature a fully differential input with a nominal full-scale range equal to twice the applied vref voltage. those devices with differential inputs have a nominal full scale range equal to twice the applied vref voltage. each input swings vref volts (peak-to- peak), 180 out of phase from one another for a total differential input of 2*vref (refer to figures 23 and 24). differential signaling offers several benefits over a single-ended input, such as: ? doubling of the full-scale input range (and therefore the dynamic range) ? improved even order harmonic distortion ? better noise immunity due to common mode rejection figure 24 shows the relationship between the reference voltage and the full-scale differential input range for two different values of vref. note that the common-mode input voltage must be maintained within 200mv of vref/2 for differential inputs. those devices with singled-ended inputs have a ground- referenced peak-to-peak input voltage span equal to the reference voltage. figure 21. ideal transfer characteristics, differential input figure 22. ideal transfer characteristics, single-ended input figure 23. differential input signaling figure 24. relationship between vref and full-scale range for differential inputs
ISL26320, isl26321, isl26322, isl26323, isl26324, isl26325, isl26329 14 fn8273.0 june 8, 2012 input multiplexer the input of the multiplexer connects the selected analog input pins to the adc input. a proprietary sampling circuit significantly reduces the input drive requirements, resulting in lower overall cost and board space in addition to improved performance. note that the input capacitance is only 2-3pf during the sampling phase, changing to 40pf during the settling phase, resulting in an average input current of 2.5 a and an effective input capacitance of only 4pf. see figure 26. voltage reference input an external reference voltage must be supplied to the vref pin to set the full-scale input range of the converter. the vref input on these devices can accept voltages ranging from 2v (nominal) to vdd, however, they are specified with vref at a voltage of 5v with vdd at 5v. note that exceeding vdd by more than 100mv can forward bias the esd protection diodes and degrade measurement accuracy due to leakage current. a lower value voltage reference must be used if the device is operated with vdd at voltages lower than 5v. if the vref pin is tied to the vdd pin, the vref pin should be decoupled with a local 1 f ceramic capacitor as described in a later paragraph. figures 27 and 28 illustrate possible voltage reference options for these adcs. figure 27 uses the precision isl21090 voltage reference, which exhibits exceptionally low drift and low noise. the isl21090 must be powered from a supply greater than 4.7v. figure 28 illustrates the isl21010 voltage reference used with these adcs. the isl21010 series voltage references have higher noise and drift than the isl21090 devices, but operate at lower supply voltages. therefore, these devices can readily be used when these sar adcs operate with vdd at voltages less than 5v. the outputs of isl21090 or the isl21010 devices should be decoupled with a 1 f ceramic capacitor. a 1 f, 6.3 v, x7r, 0603 (1608 metric) mlcc type capacitor is recommended for its high frequency performance. the trace length from the vref pin to this capacitor and the voltage reference output should be as short as possible. the ISL26320 and isl26323 devices (packaged in 8 pin soic packages) derive their voltage reference from the vdd pin. to achieve best performance, the vdd pin of these devices should be bypassed with the 1 f ceramic capacitor mentioned above. power-down/standby modes in order to reduce power consumption between conversions, a number of user-selectable modes can be utilized by setting the appropriate bits in the configuration register. auto power-down (pd0 = 0) reduces power consumption by shutting down all portions of the device except the oscillator and digital interface after completion of a conversion. there is a short recovery period after cnv is asserted low (150 s with external reference). in auto sleep mode (pd1 = 1), the device will automatically enter the low-power sleep mode at the end of the current conversion. recovery from this mode involves only 2.1 s and may offer an alternative to power-down mode in some applications. output data format the converter output word is delivered in two?s complement format in differential input mode, and straight binary in single-ended input mode of operation respectively, all msb-first. input exceeding the specified full-scale voltage results in a clipped output which will not return to in-range values until after the input signal has returned to the specified allowable voltage range. data must be read prior to the completion of the current conversion to avoid conflict and loss of data, due to overwriting of the new conversion data into the output register. figure 25. relationship between vref and full-scale range for single-ended inputs figure 26. input sampling operation input voltage offset error ac error total error dc error settling error and noise sampling phase settling phase
ISL26320, isl26321, isl26322, isl26323, isl26324, isl26325, isl26329 15 fn8273.0 june 8, 2012 figure 27. precision voltage reference for +5v supply 1 2 3 4 8 7 6 5 dnc vin comp gnd dnc dnc vout trim 0.1 f vdd 1 f (see text) 2.5v vref 0.1 f bulk + 5v isl21090 isl2631x isl2632x figure 28. voltage reference for +2.7v to +3.6v, or for +5v supply vdd 1 f (see text) vref 0.1 f bulk + +2.7v to +3.6v isl21010 gnd vin vout 1 2 3 0.1 f 1.25, 2.048 or 2.5v or +5v isl2631x isl2632x figure 29. voltage reference for ISL26320/isl26323 is derived from vdd vdd 1 f (see text) bulk +2.7v to +5v ISL26320 isl26323 table 1. output codes - differential input voltage two?s complement (12-bit) >(vfs-1.5 lsb) 7ff vfs-1.5 lsb 7ff ... 7fe -0.5 lsb 000 ? fff -vfs +0.5 lsb 801 ? 800 note: vfs in the table above equals the voltage between ain+ and ain-. differential full scale is equal to 2* vref. table 2. output codes - single-ended input voltage binary (12 bit) >ain-1.5 lsb fff ain-1.5 lsb fff ? ffe 0.5 lsb 001 ? 000 <0.5 lsb 000 note: single-ended full scale is equal to vref.
ISL26320, isl26321, isl26322, isl26323, isl26324, isl26325, isl26329 16 fn8273.0 june 8, 2012 serial digital interface the ISL26320/21/22/23/24/25/29 family utilizes an spi- compatible interface to set the device configuration and read conversion data. this flexible interface provides 3 modes of operation: reading after conversion (rac), reading during conversion (rdc), and reading spanning conversions (rsc), with an additional option providing an end of conversion (eoc) indication on the sdo output in all 3 modes. the choice of operating mode is determined by the timing of the signals on the serial interface. the interface consists of the data clock (sclk), serial digital input (sdi), serial digital output (sdo), and the conversion control input (cnv). from the idle state (after completion of a prior conversion), a high-to-low transition on cnv indicates the beginning of input signal acquisition, with the conversion then initiated by a subsequent low-to-high transition. when cnv is low, input data presented to sdi is latched on the rising edge of sclk. output data will be present at sdo on the falling edge of sclk. sdo is in the high-impedance state whenever cnv is high, and activity on sclk should be avoided during this time to avoid corruption of the conversion process. sclk should be low when cnv is high. during the nth conversion, output data indicates the conversion data and configuration settings for the n-1th conversion, while the current configuration settings apply to the n+1th conversion. in order to minimize errors due to digital noise coupling, there should be no activity on the serial interface after the specified t data period. data should be read before the conversion is completed to avoid the newer results being overwritten resulting in a permanent loss of data. reading after conversion mode without eoc in this mode, data transfer always occurs during the acquisition phase, supporting the widest variety of interface data rates. figure 30 depicts a timing waveform in this mode. from idle, the device enters the acquisition phase when cnv is taken low. sdo emerges high from a high-impedance state, waiting for an sclk to present the msb of the current output data word. the configuration settings can be updated using sdi and at the same time previous conversion results can be read from sdo. after the communication is completed or the required acquisition time (t acq ) has elapsed ? whichever is later ? cnv transitions high indicating the start of conversion. cnv must be held high continuously for a minimum of 3.6 s (at 250ksps) so that the conversion is completed without enabling eoc. subsequently cnv may be asserted low at any time so that the next acquisition phase can begin. this method is suitable for hosts which operate with lower frequency sclk. note that when using slower spi rates the data transfer time can exceed the minimum acquisition time, which will limit the conversion throughput to less than the maximum specified rate. for example, a 12-bit data transfer takes 12 s with a 1mhz spi clock. this adds to the 3.6 s conversion time for an effective throughput of 64ksps. reading during conversion mode without eoc from idle, the user initiates the input signal acquisition mode by taking cnv low, and then initiates a conversion after t acq by pulsing cnv high. after the conversion starts, data is exchanged on the serial interface while cnv is held low (as shown in figure 31). cnv must also be asserted high before t data to avoid enabling eoc. this method is ideal for hosts with high sclk communication rates to operate the device at the highest conversion rates. at the end of conversion the device enters the idle state. after the host is certain that the conversion is completed (3.6 s after conversion is initiated at 250ksps) a new acquisition can be initiated by pulling cnv low which will initiate the acquisition state. reading spanning conversion mode without eoc in applications desiring slower interface data rates and while still maintaining maximum possible throughput, rsc mode can be used to transfer data during both the acquisition and conversion phases, as shown in figure 32. data exchange begins during the acquisition phase until cnv is asserted high to initiate a conversion and sdo returns to the high-impedance state, interrupting the exchange. after cnv is returned low, sdo will return to the state prior to the cnv pulse in order to avoid data loss. once again data exchange occurs when cnv is low. cnv must be asserted high before t data in order to avoid enabling eoc. at the end of conversion the device enters the idle state. after the host is certain that the conversion is completed (3.6 s after conversion is initiated at 250ksps) a new acquisition can be initiated by pulling cnv low, which will take the device back to acquisition state from idle state.
ISL26320, isl26321, isl26322, isl26323, isl26324, isl26325, isl26329 17 fn8273.0 june 8, 2012 figure 30. timing diagram for reading after conversion mode, without eoc figure 31. timing diagram for reading during conversion mode, without eoc figure 32. timing diagram for reading spanning conversion mode, without eoc
ISL26320, isl26321, isl26322, isl26323, isl26324, isl26325, isl26329 18 fn8273.0 june 8, 2012 reading after conversion mode, with eoc in this mode (figure 33), after cnv is asserted low to start input acquisition, a data exchange is executed by sclk during the acquisition period. cnv is asserted high briefly to initiate a conversion, forcing sdo to a high-impedance state. sdo returns high when cnv is asserted low during the entire conversion period. at the end of conversion, the device asserts sdo low to indicate that the conversion is complete. this may be used as an interrupt to start the acquisition phase. it should be noted (as indicated in figure 33) that an additional pulse on cnv is required at the end of conversion to take the part back to acquisition from idle state. as discussed in the ?reading after conversion mode without eoc? section, the acquisition time (t acq ) may limit the conversion throughput at slower spi clock rates. reading during conversion mode, with eoc from idle, a falling edge on cnv initiates the acquisition mode, and then a rising edge initiates a conversion. after the conversion is initiated, cnv is asserted low once again. data exchange across sdi and sdo can proceed while cnv is low, again observing the requirements of the t data period in order to minimize the effects of digital noise on sensitive portions of the conversion. in this mode, an additional pulse is required on sclk after the completion of the data exchange, to transition sdo to the high-impedance state. later, sdo is asserted low by the device indicating end of conversion. the device then returns to idle. the falling edge of sdo may be used as an interrupt to start the acquisition phase. see figure 34. reading spanning conversion mode, with eoc after initiating an acquisition by bringing cnv low, the user begins exchanging data as previously mentioned, until cnv is asserted high to initiate a conversion and sdo returns to a high-impedance state, interrupting the exchange. and, after cnv is returned low, sdo will return to the state prior to the cnv pulse in order to avoid losing data interrupted by the conversion pulse. see figure 35. the user should take care to observe the t data period in order to minimize the effects of digital noise on sensitive portions of conversion. after completion of the data exchange, an additional pulse on sclk forces sdo to a high-impedance state. at the end of conversion, the device asserts sdo low indicating the end of conversion. the device then returns to idle, waiting for a pulse on cnv to initiate a new acquisition cycle. accessing the configuration register during data readback the configuration register contains the channel address of the current conversion data. the contents can be accessed during a normal data output sequence by continuing to clock data from sdo if the register readback mode is enabled. both 12-bit output data words and the 16-bit configuration word are output in 28 sclk periods, as shown in figure 36, which demonstrates an example sequence. note that sdo goes into the high-impedance state when cnv is high. the configuration register can be read during any read sequence by generating the additional sclks, with the restriction that the sequence must be completed prior to the end of the current conversion. this will prevent loss of data due to overwriting of the new conversion data into the output and configuration registers. figure 33. timing diagram for reading after conversion mode with eoc on sdo output
ISL26320, isl26321, isl26322, isl26323, isl26324, isl26325, isl26329 19 fn8273.0 june 8, 2012 figure 34. timing diagram for reading during conversion mode with eoc on sdo output figure 35. timing diagram for reading spanning conversions mode with eoc on sdo output figure 36. timing diagram for reading after conversion with register readback, without eoc
ISL26320, isl26321, isl26322, isl26323, isl26324, isl26325, isl26329 20 fn8273.0 june 8, 2012 device configuration registers the input multiplexer channel select and power management features are controlled by loading the appropriate bits into the 16-bit configuration register through the serial port, msb-first, as shown below. the first two load bits ld1-ld0 must be set to ?11? in order to perform a register update: any other setting will leave the register unchanged. changes to the configuration register will be implemented internally immediately following the completion of the current conversion, or require a dummy conversion in order to take effect. also, in the case of all power management features, a recovery time will be incurred when returning to normal operation, as indicated. power management modes in all spi interface modes (rac, rdc, etc.) the device has three states of operation: acquisition, conversion and idle. power management modes decide the state of the adc in idle mode and are selected by the pm bits in the configuration register as shown in table 3 and table 4. in the default mode (continuous operation) the adc is fully powered in the idle state and can be taken back to the acquisition state instantaneously. in this mode the adc can be operated with maximum throughput and hence is ideally suitable for applications where the adc is operated continuously. in auto sleep mode the isl263xx will be in a sleep state consuming less than 0.4ma. however, it should be noted that the requirements on t acq are more stringent in auto sleep mode since the device must wake up and then perform the acquisition. in auto power down mode (as selected by pm bits) the adc will be in power-down condition during the idle period, consuming less than 5 a of current. wake-up time takes 150 s. the acquisition time (t acq ) must be increased to account for this delay. the power management modes provide a high degree of flexibility in trading average power consumption versus the required throughput. significant power savings can be achieved by operating in either auto sleep mode or auto power-down mode depending on the throughput requirements. table 3. configuration register bit 15 (msb) 14 13 12 11 10 9 8 ld1 ld0 addr2 addr1 addr0 pm1 pm0 unused bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) rgrd unused table 4. configuration register 2 bit(s) description 15:14 register load word, set to ?11? to update registers, otherwise previous settings are retained. 13:11 multiplexer channel select word addr2:0. 000h: channel ain0 (single-ended input devices) or ain0+/ain0- (differential input devices) 001h: channel ain1 or ain1+/ain1- 010h: channel ain2 or ain2+/ain2- 011h: channel ain3 or ain3+/ain3- 100h: channel ain4 101h: channel ain5 110h: channel ain6 111h: channel ain7 10:9 power management configuration control 00h: auto power-down mode. device will go into power-down mode automatically at the end of the next conversion cycle. 01h: continuous operation mode (default). device remains fully powered at all times. 1xh: auto sleep mode. device will enter reduced-power sleep mode automatically at the end of the next conversion cycle. a "1" in pm1 overrides the setting in pm0. 8 unused 7 register readback mode. "1" means register readback is enabled resulting in configuration settings to be output along with conversion results. "0" (default) mode of operation register settings are not output. 6:0 unused
ISL26320, isl26321, isl26322, isl26323, isl26324, isl26325, isl26329 21 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www .int er sil.com/design/q uality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www .int er sil.com fn8273.0 june 8, 2012 for additional products, see www .int er sil.com/pr oduct_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semiconductors. the company's product s address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog signal processing functions. go to www .int er sil.com/pr oducts for a complete list of intersil product families. for a complete listing of applications, related documentation and related parts, please see the respective device information p age on intersil.com: ISL26320 , isl2632 1 , isl26322 , isl26323 , isl2632 4 , isl26325 , isl26329 . to report errors or suggestions for this datasheet, please go to: www .int er sil.com/ask our staf f fits are available from our website at: http://rel.int er sil.com/repor ts/sear revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change june 8, 2012 fn8273.0 initial release.
ISL26320, isl26321, isl26322, isl26323, isl26324, isl26325, isl26329 22 fn8273.0 june 8, 2012 package outline drawing m16.173 16 lead thin shrink small outline package (tssop) rev 2, 5/10 0.09-0.20 see detail "x" detail "x" typical recommended land pattern top view side view end view dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 per side. dimension does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 per side. dimensions are measured at datum plane h. dimensioning and tolerancing per asme y14.5m-1994. dimension does not include dambar protrusion. allowable protrusion shall be 0.08mm total in excess of dimension at maximum material condition. minimum space between protrusion and adjacent lead is 0.07mm. dimension in ( ) are for reference only. conforms to jedec mo-153. 6. 3. 5. 4. 2. 1. notes: 7. (0.65 typ) (5.65) (0.35 typ) 0.90 +0.15/-0.10 0.60 0.15 0.15 max 0.05 min plane gauge 0-8 0.25 1.00 ref (1.45) 16 2 1 3 8 b 1 3 9 a pin #1 i.d. mark 5.00 0.10 6.40 4.40 0.10 0.65 1.20 max seating plane 0.25 +0.05/-0.06 5 c h 0.20 c b a 0.10 c - 0.05 0.10 c b a m
ISL26320, isl26321, isl26322, isl26323, isl26324, isl26325, isl26329 23 fn8273.0 june 8, 2012 package outline drawing m8.15 8 lead narrow body small outline plastic package rev 4, 1/12 detail "a" top view index area 123 -c- seating plane x 45 notes: 1. dimensioning and tolerancing per ansi y14.5m-1994. 2. package length does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 3. package width does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 5. terminal numbers are shown for reference only. 6. the lead width as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 7. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. 8. this outline conforms to jedec publication ms-012-aa issue c. side view ?a side view ?b? 1.27 (0.050) 6.20 (0.244) 5.80 (0.228) 4.00 (0.157) 3.80 (0.150) 0.50 (0.20) 0.25 (0.01) 5.00 (0.197) 4.80 (0.189) 1.75 (0.069) 1.35 (0.053) 0.25(0.010) 0.10(0.004) 0.51(0.020) 0.33(0.013) 8 0 0.25 (0.010) 0.19 (0.008) 1.27 (0.050) 0.40 (0.016) 1.27 (0.050) 5.20(0.205) 1 2 3 4 5 6 7 8 typical recommended land pattern 2.20 (0.087) 0.60 (0.023)

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